1. Field of the Invention
The present invention relates to a device mounting board and a manufacturing method therefor, and a semiconductor module.
2. Description of the Related Art
A known method of surface-mounting a semiconductor device is flip-chip mounting in which solder bumps are formed on electrodes of the semiconductor device and the solder bumps are connected to an electrode pad of a printed wiring substrate. For example, a CSP (Chip Size Package) is known as a structure employing the flip-chip mounting.
In a semiconductor module having a CSP structure, thermal stress occurs between a printed wiring substrate and the semiconductor module due to a difference in thermal expansion coefficients between the printed wiring board and the semiconductor module in a usage environment or the like. To cope with this, a structure is known where a plurality of recesses are provided on the wiring in approximately the same direction in which a semiconductor chip expands and contracts due to the thermal stress, in such a manner as to be slightly apart from each other. This structure is used to reduce the thermal stress occurring between the printed wiring board and the semiconductor module due to a difference in thermal expansion coefficients between the printed wiring board and the semiconductor module in a usage environment and the like.
With miniaturization and higher performance in electronic devices in recent years, demand has been ever greater for further miniaturization of semiconductor devices used in the electronic devices. With such miniaturization of semiconductor devices, it is of absolute necessity that the pitch of electrodes to enable mounting on the printed wiring board be made narrower. With this flip-chip method, however, there are restrictive factors for the narrowing of the pitch of electrodes, such as the size of the solder bump itself and the bridge formation at soldering. As one structure used to overcome these limitations, known is a structure where a bump structure formed on a substrate is used as an electrode or a via, and the electrodes of the semiconductor device are connected to the bump structure by mounting the semiconductor device on a substrate with an insulating resin, such as epoxy resin, held between the semiconductor device and the substrate.
As another structure used to overcome these limitations, known is a structure where a bump structure formed on a wiring layer made of a metal such as copper is used as an electrode or a via, and the electrodes of the semiconductor device are connected to the bump structure by mounting the semiconductor device on a substrate with an insulating resin, such as epoxy resin, held between the semiconductor device and the substrate.
Also, a structure is known where a circuit terminal electrode and a metal-pasted bump are covered with a Ni plating layer and an Au plating layer, in a structure where the metal-pasted bump is projected from the circuit terminal electrode provided on one main surface of a substrate toward a sealing member such as epoxy resin.
In the above structure where the bump structure formed on a substrate is connected to the electrode of a semiconductor device, there is concern that the thermal stress caused by a difference in thermal expansion coefficients between the substrate and the semiconductor device may be concentrated on the bump structure. As a result, cracks may be caused in the bump structure and therefore the reliability of connection between the semiconductor device and the printed wiring board may drop.
Also, in the above structure where the bump structure formed on a wiring layer is connected to the electrode of a semiconductor device, a metal such as conductive copper is generally used for a material that constitutes the bump structure. Accordingly, the thermal expansion coefficient differs in between the wiring layer or bump structure and the insulating resin layer. As a result, the thermal stress occurs due to the change in temperature in the heat treatment or usage environment and therefore this thermal stress may be concentrated on the bump structure. As a consequence, cracks may be caused in the bump structure and therefore the reliability of connection between the semiconductor device and the printed wiring board may drop.
Also, when the above-described structure where the electrode and the bump are covered with a Ni plating layer and an Au plating layer is applied to a structure where a device mounting board and a semiconductor device are stacked together by press-bonding a bump structure provided on a wiring layer of the device mounting board and an electrode of the semiconductor device with an insulating resin layer held between the bump structure and the semiconductor device, the connection reliability between the wiring layer and the bump structure improves. However, in the structure where the device mounting board and the semiconductor device are stacked together, the thermal stress that occurs due to the change in temperature in the heat treatment or usage environment may be concentrated on the neighborhood of an interconnector between a bump structure and the electrode of the semiconductor device. Then the connection reliability between the bump structure and the electrodes of the semiconductor device may drop.